The optimum pipeline depth of a microprocessor for low energy consumption

Abstract

The number of pipeline stages that minimize the energy consumption in pipeline processors is studied based on a mathematical performance model, and the conditions are examined. We examine the Energy Per Instruction (EPI) when given the clock cycle time and the minimum power supply voltage required for operation where the execution times per instruction will be equal for processor models having different numbers of stages. In processors targeting low energy consumption, the optimum number of pipeline stages is five or less when the rate of increase in the circuit load capacitance is 10% as the number of stages increases. Pipeline hazards such as branch prediction misses have a substantial effect on the energy consumption and the optimum minimum number of stages. The latch overhead time, which depends on the circuit design technology, has little effect. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 88(1): 1–11, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20098