Design and Analysis of Floating Point and Galois Field Multipliers Using Wave-Pipelining

Abstract

This paper deals with the Design and Analysis of Floating point and Galois field multipliers using a pipelining technique called “Wave pipelining”. Wave pipelining is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than conventional pipelining techniques. Wave pipelining can improve the throughput of a logic circuit while avoiding some of the overheads of traditional pipelining. Multiplication plays a very important role in the signal processing application in signal processing, multiplication and shifting operations involves larger computation time. Hence making the multiplier to operate at higher speed will increase the performance of signal processing. Galois Field Theory (GFT) deals with binary numbers, has the properties of a mathematical “field,” and are finite in scope. Many Galois operations match those of regular math. Addition and multiplication are the common Galois operations, and logarithms, particularly, are handy for checking multiplication results. Galois Field multipliers have been widely used in coding theory and cryptography. Finally the synthesis reports of different pipelining stages of both the multipliers have been tabulated by implementing the algorithm in Xilinx Spartan 3E FPGA board.