On the design of reconfigurable multipliers for integer and Galois field multiplication

Abstract

Multiplication is a vital function for practically any DSP system. Some common DSP algorithms require different multiplication types, specifically integer or Galois Field (GF) multiplication. Since both functions share similarities in their structures, the potential is given for efficiently combining them in a single reconfigurable VLSI circuit, leading to competitive designs in terms of area, performance, and power consumption. This will be analysed and discussed in detail for 10 reconfigurable multiplier alternatives that are based on different strategies for the combination of integer and GF multiplication. Each result is compared to a reference architecture, showing area savings of up to 20% at a marginal increase in delay, and an increase in power consumption of 25% and above. This gives evidence that function-specific reconfigurable circuits can achieve considerable improvements in at least one design objective with only a moderate degradation in others. From this perspective, function-specific reconfigurable circuits can be considered feasible alternatives to standard ASIC solutions.