Flexible VLSI architectures for Galois field multipliers

Abstract

Galois field (GF) multipliers play a major role in the engineering applications such as cryptography and error correcting codes. This paper proposes systolic vector m-bit GF(p) and GF(2m) multipliers (m=log2p), where four numbers of m2-bit GF multiplications can be done in parallel. Similarly, twelve and sixteen numbers of GF(2m4) and m4-bit GF(p) multiplications can be done in parallel respectively. Also, this paper proposes non vector flexible GF(2m) and m-bit GF(p) multipliers, where the m can be varied from 2 to the maximum allowable value. Our proposed systolic vector parallel GF(216) multiplier achieves 95.8% of improvement in throughput over reconfigurable bit serial design [7]. Similarly, the proposed systolic vector parallel 16-bit GF(p) multiplier achieves 82.5% of improvement in throughput over reconfigurable bit serial design [23] using 45nm CMOS technology.