Alpha-SER modeling and simulation for sub-0.25 μm CMOS technology

Abstract

Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging materials were first observed on DRAMs. While terrestrial cosmic rays also cause soft errors and dominate logic circuit soft-error rate (SER), alpha-SER contributes significantly to SRAM circuit total SER and increases at a higher rate as processing technology advances to sub-0.25 /spl mu/m feature sizes where even logic nodes become susceptible to alpha strikes. In sub-0.25 /spl mu/m CMOS and beyond, with continuous reduction in supply voltage, decrease in node capacitance, and increase in chip size and transistor count, alpha-SER has become a major reliability concern for logic products. As complex logic products such as microprocessors have numerous circuit types and sizes, accurate and efficient prediction of product SER by comprehending both microscopic charge collection physics and circuit response is both critical and a challenging task. This paper presents a comprehensive modeling and simulation approach, including: (1) circuit critical charge (Qcrit) simulation methodology, (2) compact model for alpha strike charge generation and collection, and (3) statistical algorithms for FIT (failure-in-time) rate simulation. We also present compact model calibration methods and validation using Lawrence Livermore National Lab alpha beams as well as experimentally measured FIT rates of SRAMs in three technology generations. This paper reports the alpha-SER saturation effect, which is extremely critical for future technology planning. Moreover, many of the concepts and models discussed here can be extended to neutron-SER prediction.