Transistor Sizing in Order to Hardening CMOS circuit against Soft Error

Abstract

to the shrinking of feature size and reduction in supply voltages, nano scale circuits have become more susceptible to radiation induced transient faults. Transient faults caused by radiation are becoming a major barrier to robust system design manufactured at technology nodes like 90nm, 65nm or smaller. A single event upset (SEU) may cause a bit flips in some latches or memory elements, thereby altering the state of the system, leading to a soft error. Soft errors in memory have traditionally been a much greater concern than soft errors in logic circuits. In this paper we propose an accurate and prompt approach in order to finding minimum transistor size to hardening CMOS circuits against SEU. One of the hardening CMOS circuit methods against SEU is transistor sizing; a large transistor can dissipate the injected charge as quickly as it is deposited so that the transient does not achieve sufficient magnitude and duration to propagate to gates in fan out. Most hardening methods based on transistor sizing have high area overhead. Since the suggested method at this paper is obtained minimum transistor size for hardening, the optimization of area will be done. experimental results show that present mathematical model results are agree well with SPICE simulations, while allowing for very fast analysis.