Advanced Fanout Embedded Bridge Packaging Technology for Chiplets Integration

Abstract

The increasing amount of data from all sectors driven by digital transformation is raising a problem of operational and storing cost of the data. Meanwhile, the exponential cost leaps of silicon scaling, the unfordable increasing of Si die size over reticle limit and unsustainable computer energy exceeding the world’s energy production have created an inflection point for semiconductor industry. It has driven the development of More-Than-Moore to augment increased device and system performance. Chiplets integration provides more flexible mix-and-match systems to accelerate performance and power efficiency. It is driving the development of advanced packaging technology to enable heterogeneous chiplets integration with separate designs and different manufacturing process nodes within a single package for yield improvement, IP reuse, performance and cost optimization, as well time to market reduction. Several advanced packaging technologies have been developed and used widely to integrate multi-chips with fine line/space interconnections, such as 2.5D Si TSV interposer, Fanout RDL (re-distribution layer) and EMIB (Embedded Multi-die Interconnect Bridge). Different packaging technologies have different sweet spots to fulfill various applications depending on the device design and performance requirements. In ASE, we have developed and introduced FOCoS (FanOut Chip on Substrate) chip first (FOCoS-CF) and FOCoS chip last (FOCoS-CL) technologies by using RDL interconnect for chiplets integration. However, due to the inherent fanout RDL process limitation, it has hit the bottleneck to manufacture RDL with higher layer counts (> 6 layers) and finer Line/Space (L/S < 1um/1um) for the applications that require high density die to die connections, high input/output (I/O) counts and high-speed signal transmitting. In this paper, a new FOCoS technology named as FOCoS embedded Si bridge (FOCoS-B) has been developed for high density die to die interconnect with RDL L/S < 1um/1um chipets integration for HPC application. The FOCoS-B packaging technology enables the USR (Ultra Short Reach) interconnection between die to die by embedded a small Si die in fanout RDL interposer. The small Si die play an interconnection bridge role between chiplets with L/S 0.8um/0.8um. Two FOCoS-B test vehicles (TVs) will be introduced in this study. One TV named as TV-1 is integrated by two chiplets of 1 ASIC die and 1 HBM2e with 1 Si bridge die to form a fanout module, which it is subsequently assembled on a FCBGA package with body size of 40x30mm2. Another TV listed as TV-2 is composed of two identical fanout modules, which are assembled on one FCBGA substrate with body size of 78x70mm2 in MCM (multi-chip-module) arrangement. The fanout module for TV-2 is integrated by 1 ASIC and 4 HBM2e with 4 bridge dies. TV-2 will have total 10 chiplets (2 ASICs and 8 HBM2e with 8 Si bridge dies). The process flow for FOCoS-B will be illuminated. The process DOE and the impact on warpage will be discussed. Furthermore, the reliability validations on two TVs will also be demonstrated. Finally, the comparison on warpage among different FOCoS solutions (FOCoS-B, FOCoS-CL and FOCoS-CL) for chiplets integration have been presented. The results indicated that the material selections and property compatibilities among the multi-layer stacked structures (Si die, RDL, Molding compounds, Underfill) play critical roles in warpage control in FOCoS-B processes. The package warpage of FOCoS-B and FOCoS-CL has showed similar behaviors. FOCoS-CF showed slightly high package warpage than that of FOCoS-B. The results also revealed that FOCoS-B has provided a wide choice and flexibility for multi bridge dies integration successfully for HPC application.