Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories

Abstract

ECC techniques have been widely used for protecting flash memory endurance and permanent faults. Therefore, the fabrication yield and reliability can be enhanced. However, if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC techniques, the effectiveness of the protection will decrease rapidly. In this paper, adaptive ECC techniques based on address remapping are proposed to cure this drawback. We can change the logical-to-physical address mapping of the page buffer such that faulty cells can be evenly distributed into different codewords. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the remapping algorithm and evaluating control words. Based on the control words, faulty cells can be evenly distributed into different codewords. To conduct the address remapping, a novel page buffer design is also proposed. A simulator is developed to evaluate the hardware overhead, repair rate, effective yield, and reliability. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.