Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories

Abstract

Error correction code (ECC) and built-in self-repair (BISR) techniques have been widely used for improving the yield and reliability of embedded memories. The targets of these two schemes are transient faults and hard faults, respectively. Recently, ECC is also considered as a promising solution for correcting hard error to further enhance the fabrication yield of memories. However, if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC scheme, the protection will become void. In order to cure this drawback, efficient logical to physical address remapping techniques are proposed in this paper. The goal is to reconstruct the constituent cells of codewords such that faulty cells can be evenly distributed into different codewords. A heuristic algorithm suitable for built-in implementation is presented for address remapping analysis. The corresponding built-in remapping analysis circuit is then derived. It can be easily integrated into the conventional built-in self-repair (BISR) module. A simulator is developed to evaluate the hardware overhead and repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.