Active clamp ESD protection in complementary BICMOS process

V.A Vashchenko,P.J Hopper

doi:10.1109/icsict.2010.5667707

Active clamp ESD protection in complementary BICMOS process

V.A Vashchenko, P.J Hopper

https://doi.org/10.1109/icsict.2010.5667707

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Publication Date: Nov 1, 2010

Citations: 1

Affiliation: Texas Instruments (United States)

#Complementary BICMOS Process #Low Voltage CMOS + Show 8 more

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Abstract

Abstract A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by simulation and experimentally validated. The new clamp is composed from stacked NMOS driver to achieve appropriate voltage tolerance and power BJT. Both NPN and PNP- based versions of the clamp are compared to the stacked NMOS clamp.

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