A wet etching approach for the via-reveal of a wafer with through silicon vias

Abstract

Through silicon vias (TSVs) increase the interconnect bandwidth, reduce the RC delay and improve the power efficiency because the TSVs shorten vertical signal paths greatly. The process of via-reveal on the wafer backside is one of key steps for a successful implementation of 3D-IC stacking using the TSV technique, e.g. the via-first and via-middle TSV integrations. Instead of using a full chemical mechanical polish (CMP) or a dry etch process, we proposed a method of two-step full wet etching in this study. The solutions of HF/HNO3 and tetramethyl ammonium hydroxide (TMAH) are used in the two steps, respectively. The second etching step is only necessary for the wafers with a large thickness variation. Based on the full wet etching mechanism of silicon, we designed experiments to obtain the satisfied etching rate, selectivity and etching profile with optimized parameters. Using the approach, the via-reveal process was conducted for wafers with different incoming remain silicon thickness (RST) profiles. The sample characterization manifest that the present full wet etching process is well-controlled, efficient and cost effective.