Development of 300 mm TSV interposer with redistribution layers on both sides using MEMS processes

Abstract

A Silicon interposer with through silicon via (TSV) has become important key components of 3D integration. It is used as an intermediate carrier and a wiring device for IC components like logics, memories, sensors, and so on. Due to wiring with custom design on front and back side, a TSV interposer enables to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. However the key problem facing the TSV interposer is a cost issue. In this paper, TSV based interposer fabrication process for 3D packaging has been presented and the process uniformity with 300 mm wafer was evaluated for cost reduction and yield improvement. TSVs of 50 μm in diameter were formed on a 300 mm wafer of 500 μm in thickness by deep reactive ion etching (DRIE) process and the vias were isolated with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer, followed by barrier/seed layers of Ti/Cu deposition. The TSVs were filled with solid Copper (Cu) using electroplating of optimized periodic pulse reverse (PPR) and chemical mechanical polishing (CMP) process also developed to remove the Cu overburden. For void free TSV interconnects and uniformity improvement, the Cu electroplating process was simulated with 300 mm wafer and developed with the simulation result. The process uniformity of Cu electroplating was equivalent to the simulation result and void free TSV interconnects were successfully formed. The RDL lines were formed on the TSV by Cu electroplating and the RDL lines were electrically isolated with the dielectric PBO film. The TSV interposer of 500 μm thickness has been fabricated successfully with MEMS processes and the vias were in good conductivity from the top to the bottom. The distribution of via etching process, via filling process and CMP process were evaluated and no significant failures were observed. The uniformity of the via etching process was less than 5 %. The distribution of Cu overburden thickness was less than 100 μm. The dishing amount of Cu via after CMP was less than 10 μm. The electric characteristics of RDL leakage current and via resistance were measured. The leakage current between RDL lines was about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> A so that the RDL lines were electrically isolated. The average value of via resistances was 2.43 ohm and via resistances were normally distributed with tangible electric characteristics. The fabrication process of TSV based silicon interposer with 300 mm wafer by MEMS processes was successfully demonstrated in terms of mass production.