Abstract

This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

Highlights

  • For competitive markets like consumer electronics or telecommunications, application-specific integrated circuit (ASIC) often lacks flexibility and programmability

  • This paper presents a novel instruction set architecture (ISA) named VS-ISA to the THUASDSP2004 architecture, which is a video specific digital signal processor (DSP) architecture for Application specific instruction processor (ASIP) design and scalable for ISA update [7]

  • Comparing with the basic architecture, the critical path of modified function units increase from 1.1% to 5.1%, and the modified function unit area increases from 4.3% to 7.3%

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Summary

INTRODUCTION

For competitive markets like consumer electronics or telecommunications, application-specific integrated circuit (ASIC) often lacks flexibility and programmability. By exploiting data parallelism using application-specific instructions, configurable ASIPs gain significant performance improvement. More recent standards introduce new encoding tools to offer improved performance in terms of picture quality at certain bitrate. This does not mean that older standards become obsolete. Existing single instruction multidata (SIMD) multimedia extensions and DSPs support various instructions to execute packed operations between two registers. These operations are used for various video signal processing, such as motion estimation and compensation, discrete cosine transform (DCT), and inverse-DCT (IDCT).

THUASDSP2004 ARCHITECTURE OVERVIEW
VIDEO APPLICATION CHARACTERISTICS
VIDEO SPECIFIC INSTRUCTION SET ARCHITECTURE
Proposed instructions for motion estimation
Proposed instructions for integer transform
Proposed instructions for quantization and dequantization
Hardware modification for proposed instructions
PERFORMANCE EVALUATION
Findings
CONCLUSION AND FUTURE WORK
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