A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch

Abstract

With the continuous technology scaling of integrated circuits, storage devices are more and more easily affected by soft errors. In order to improve the reliability of storage devices and reduce overhead especially in terms of power dissipation effectively, this paper proposes a Soft-Error-Immune Quadruple-Node-Upset tolerant latch (Quad-SIRI). The latch consists of two interlocked SIRI (Soft-error-immune) SRAM cells for dual modular redundancy. Considering the characteristic of radiation-induced voltage pulse, the SIRI is designed with stacked transistors to tolerate single-node-upset and reduce sensitive nodes and area overhead. Quad-SIRI latch achieves low area overhead because of fewer transistors. Quad-SIRI latch achieves low power consumption because of clock-gating technique. However, pass transistors and stacked transistors result in small critical charge of the latch. HSPICE simulation in 22nm CMOS technology shows that, compared with quadruple-node-upset tolerant latches (LCQNUSR, QNUTL and 4NUHL), Quad-SIRI latch achieves the smallest delay, power and area, at the cost of smaller critical charge. Extensive variation analysis shows that Quad-SIRI latch is less sensitive to temperature and voltage variation in terms of power consumption and less sensitive to temperature variation in terms of delay. So, compared with the existing latches, Quad-SIRI latch makes a good trade-off among delay, power, area and critical charge, and thus it is a good choice for radiation hardening by design in spaceborne applications with low energy particle striking.