Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

Abstract

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.