A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology

Abstract

With the scaling of CMOS feature size, the multi-node upset caused by radiation has become an important reliability issue of storage devices. In order to improve the robustness of the storage devices, this paper proposes a High-Speed Quadruple-Node-Upset tolerant latch (HS-QNU). The proposed HS-QNU latch consists of two single-node-upset-resilient RFCs, two single-node-upset-resilient DICEs and a clocked quadruple-input C-element. Based on the single-node-upset-resilient ability of DICE and RFC and the blocking ability of C-element, the proposed HS-QNU latch can effectively tolerate soft errors when any four internal nodes upset by transient faults at the same time. Meanwhile, the latch effectively reduces delay and power consumption by using high-speed path and clock-gating technique. Extensive SPICE simulation in 22 nm CMOS technology shows that compared with QNUTL, the proposed latch reduces delay by 30.68 %, reduces power consumption by 30.86 %, reduces power-delay-product by 52.07 %, reduces area-power-delay-product by 49.08 %, and only increases area overhead by 6.25 %. The proposed HS-QNU latch achieves good tradeoff among delay, power consumption and area. Compared with the previous hardened latches, the proposed HS-QNU latch has the best hardening ability, the highest speed and the smallest power-delay-product. The variation analysis shows that the proposed HS-QNU latch is insensitive to temperature and voltage variations.