12-Bit Clock Gated SAR-ADC for Bio-Medical Applications

Abstract

Background/Objectives: Power optimization is a critical design criterion in modern integrated circuits. The unwanted clock signals are neutralized and the reduction in power consumption is made presumable by using the clock gating technique. Methods: Analog-to-digital converters (ADCs) are important components in these systems. A widely used successive approximation register A/D converter includes an internal clock, reference, and high resolution. The number of redundant cycles is increased with improved resolutions but enhances the consumption of power. Thus, the clock gating strategy is used to substantially lower the circuit’s dynamic power consumption. The clock gating technique is implemented with a reduced number of transistors to minimize the overhead with high switching activity. Also, demonstrate no imperfection on the clock duty cycle. Findings: A 12-bit clock gated SAR register using a D-flip flop with 1.8 V supply voltage is proposed in this study for efficient biomedical applications. SAR without a clock gating technique consumes 54 mW of power and SAR with a clock gating technique consumes a power of 22.68 mW. Novelty: The clock gating technique is stipulated to minimize power consumption of clock gated SAR-ADC and improves the battery life of the portable device. Keywords: Clock gated technique; power consumption; resolution; SARADC; successive approximation register