Abstract
A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This results in high efficiency with respect to other static frequency dividers in BiCMOS technology presented in the literature. The divider topology does not use inductors, thus optimizing the area footprint: the divider core occupies 60 × 65 μm2 on silicon.
Highlights
Frequency dividers are a fundamental building block in many RF and mixed-signal high-speed systems, such as frequency synthesizers, I/Q signal generators, carrier recovery systems, SerDes systems, and time-interleaved data converters [1,2,3,4,5,6]
SiGe BiCMOS is often used in very high frequency applications, allowing the design of RF systems in D-band [9] and wireline transceivers at 100 Gbaud and beyond [10]
In this55paper, we present thetechnology, design and measurements of a static frequency dividerconsumption in commercial commercial nm SiGe that has been optimized for low power
Summary
Frequency dividers are a fundamental building block in many RF and mixed-signal high-speed systems, such as frequency synthesizers, I/Q signal generators, carrier recovery systems, SerDes systems, and time-interleaved data converters [1,2,3,4,5,6]. The evolution of technology enables faster and faster systems to be designed, with an increasing demand on higher frequency performance for all the blocks, on the other hand, there is a growing impulse to minimize the power consumption for these high frequency systems, to allow higher integration and to simplify packaging. SiGe BiCMOS is often used in very high frequency applications, allowing the design of RF systems in D-band [9] and wireline transceivers at 100 Gbaud and beyond [10]. Frequency dividers for high frequency systems in the literature are typically based on four architectures: static, dynamic, regenerative, and injection-locked dividers. Dynamic frequency dividers (DFD) achieve higher frequencies but with a smaller operating range and higher sensitivity to process variations [12]
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