A novel redundant cyclic method to improve the SFDR of SAR ADC

Abstract

A novel redundant cyclic switching method is proposed for successive approximation register (SAR) analog-to-digital converter (ADC), the proposed redundant cyclic technique can reduce the harmonic distortion caused by capacitor mismatch without trimming or complicated digital calibration. The application of this switching method to 14-bit SAR ADC is demonstrated by 1000 Monte-Carlo runs, results show that with standard deviations $$\sigma _{u}$$źu of 0.2 %($$\sigma _{0}/C_{0}$$ź0/C0=0.002), the proposed redundant cyclic switching scheme improves the average value of SNDR from 73.63 dB (11.93 ENOB) to 80.84 dB (13.13 ENOB) and the average value of SFDR is almost 20 dB better compared with the conventional switching method.