A new low-leakage T-Gate based 8T SRAM cell with improved write-ability in 90nm CMOS technology

Abstract

In this paper an innovative T-Gate based Static Random Access Memory (SRAM) cell design is proposed which improves write-ability of conventional designs in subthreshold operating region. Write-ability of proposed design is improved by cutting the feedback loop in SRAM cell and omitting the challenging inverters effect during write state by adding a T-Gate. This T-Gate is opaque during write operation and transparent for rest of operations. Due to improved write operation, it is possible to choose minimum size access transistors to remove access transistor sizing conflict of conventional 6T SRAM cell. As a result, read stability will be improved. Added T-Gate in the middle of the cell helps to better transferring both of logic-1 and 0 that leads to having full swing at the internal nodes of SRAM cell. As a result leakage power of proposed cell is improved over the previous design introduced in [1]. Simulation results show that proposed design improves leakage power of single cell by 38% at T=110°C and at VDD=500mV over that design. WNM of proposed design is increased by 188% and 62% over the cell in [1] and conventional 6T SRAM cell, respectively.