A Multimode SiGe BiCMOS 5–6 GHz Front-End IC that Enables 802.11ac Wave 2 and 802.11ax Wireless LAN Front-End Designs

Abstract

A multimode 4.9–5.9 GHz ultra-linear single chip front-end integrated circuit (FEIC) for 802.11ac and emerging multi-gigabit per second (Gbps) wireless local area network (WLAN) applications is presented. The design is based on SiGe BiCMOS and realized in a 2.0 x 2.0 x 0.5 mm3 package. The FEIC design consists of both transmit (Tx) and receive (Rx) chains, which integrates a single-pole double-throw (SPDT) Tx/Rx CMOS switch, a SiGe power amplifier (PA), and a SiGe low noise amplifier (LNA) with a CMOS bypass attenuator. The SiGe PA in the transmit chain integrates input and output matching networks, harmonic filters, out-of-band rejection filters, supply voltage regulator and multi-mode bias circuits, temperature and voltage compensated power detector with on-chip directional coupler, and CMOS-compatible enable circuitry. The PA is controlled by the on-chip temperature and voltage compensated bias controller. With a 5 V supply, the transmit chain features 31 dB gain and excellent linearity. The transmit chain can deliver 19 dBm output power with current consumption 220 mA meeting below -40 dB Dynamic Mode Error Vector Magnitude (DEVM) for 1024 QAM signals and 20 dBm with current consumption 250 mA meeting below -35 dB DEVM for 256 QAM signals. The feature of ultra-low DEVM enables the emerging 1024-QAM applications. The harmonics emissions of the transmit chain can achieve below -50 dBm/MHz, greatly exceeding FCC out-of-band emission requirements. In addition, the linearity of the transmit chain output power is well scaled with the supply voltage from 3.0 V to 5.5V and insensitive to signal modulation bandwidths as well as duty cycles. The low linearity mode features 50 mA lower current consumption comparing to the high linearity mode. With the use of digital pre-distortion (DPD), it can achieve the similar linear power with 50 mA current reduction. The integrated log detector with an on-chip directional coupler ensures the accurate power control over 24 dB with less than 0.5 dB power control inaccuracy under VSWR 3:1 mismatch, which significantly increases the dynamic range and accurate power control for the transmit path. The Rx chain features noise figure (NF) below 2.5 dB with 15 dB gain and the current consumption of 8 mA as well as 8 dBm IIP3. The receive chain also integrates an 8 dB bypass attenuator having 25 dBm IIP3 with 3uA current consumption, which can prevent the WLAN radio from saturation under high field strength illuminations. All these unique features provide a turn-key solution for the single band or dual-band 802.11ac radio front-end circuits and emerging multiple gigabits per second high linearity WLAN radio designs. Figure 1