Abstract

A triple-band CMOS power amplifier (PA) is presented. We propose a design methodology using an input matching network to support triple-band operation at 0.9, 1.8, and 2.4 GHz. We also propose an output matching network for the triple-band operation. Given that 1.8 and 2.4 GHz are the harmonic components when the PA is operating at 0.9 GHz, we design the output matching network to be switchable to suppress the harmonic components at the operating frequency. Using this switchable network, we obtain an optimum power matching point for each of the three operating frequencies. To verify the feasibility of the proposed structure, we designed a PA using a 180-nm RFCMOS process. It was measured using a wideband code division multiple access (WCDMA), Long-Term Evolution (LTE) at a 10/20-MHz bandwidth and wireless local area network (WLAN) 802.11n applications. The measured output power was 27.2/26.6 dBm, and the power-added efficiency (PAE) was 22.9%/30.6% under an adjacent channel leakage ratio (ACLR) of -33 dBc at 0.95/1.8 GHz, respectively, with a WCDMA modulation signal. In the case of an LTE modulation signal, the measured output power was 25.1/23.5 dBm, and the PAE was 27.7%/23.6% under an ACLR of −30 dBc for a 10/20-MHz bandwidth, respectively, at 1.8 GHz. The measured output power was 21 dBm, and the PAE was 20% under an error vector magnitude (EVM) of 3.98% at 2.4 GHz for a WLAN modulation signal. Based on the measured results, we successfully verified the feasibility of the proposed PA.

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