A Low-Power Wideband Transmitter Front-End Chip for 80 GHz FMCW Radar Systems With Integrated 23 GHz Downconverter VCO

Abstract

A low-power FMCW 80 GHz radar transmitter front-end chip is presented, which was fabricated in a SiGe bipolar production technology ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> =180 GHz, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> =250 GHz ). Additionally to the fundamental 80 GHz VCO, a 4:1-frequency divider (up to 100 GHz), a 23 GHz local oscillator (VCO) with a low phase noise of -112 dBc/Hz (1 MHz offset), a PLL-mixer and a static frequency divider is integrated together with several output buffers. This chip was designed for low power consumption (in total <; 0.5 W, i.e., 100 mA at 5 V supply voltage), which is dominated by the 80 GHz VCO due to the demands for high output power (≈ 12 dBm) and low phase noise (minimum -97 dBc/Hz at 1 MHz offset) within the total wide tuning range from 68 GHz to 92.5 GHz (Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> = 24.5 GHz). Measurements of the double-PLL system at 80 GHz showed a low phase noise of -88 dBc/Hz at 10 kHz offset frequency.