Abstract
A high-speed I2L gate for VLSI application has been successfully designed, characterized and demonstrated. The high-speed performance has been achieved in an oxide isolated I2L with a buried-base structure by means of a thin epitaxial layer and heavily doped extrinsic base, and characterized by 0.87 ns of minimum delay time at fan-out of 1 and 1.6 ns at fan-out of 3. The I2L characteristics have been superiorly controlled by optimizing the impurity profile with the reduced pressure epitaxy: For example, the deviation of breakdown voltage (BVCEO) is almost 10% and the deviation of delay time is less than 4%. The influence of device structure on the gate speed has been investigated and then the typical performance for the high-speed gate array which allows propagation delay time down to 3.7 ns at 275 µA/gate injection current has been obtained with the use of 3.4 µm design rule, a dual injector structure and the optimized process.
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