A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL

Abstract

A low-cost and manufacturable 3D IC substrate-less Chip-on-Wafer (CoW) package has been studied. The new structure is a result of process simplification from the production-proven Chip on Wafer on Substrate (CoWoS™) technology. It features three layers of submicron (0.8μm pitch) Cu RDL on a Si interposer. High interposer yield is ensured with the excellent FAB-grade low defect density as demonstrated from good continuity of long RDL chains. Two layers of backside RDL are used to redistribute the IO from TSV at 0.2 mm pitch to BGA at 0.6 mm pitch. With the same multi-die integration capability as in CoWoS™, the CoW package has additional advantages of lower z-height, better thermal dissipation, and lower cost. Moreover, mechanical and thermal simulations reveal a relatively greater life cycle endurance for temperature cycling on board (TCoB) test. The CoW package passed preliminary component-level reliability assessments including μHAST, HTS and TC. This provides a promising CoWoS™ alternative for lower cost and thinner package with improved thermal performance. It also possesses the flexibility to combine with fan-out technology to be fitted in applications requiring higher IO count or larger BGA pitch.