Abstract
Wafer Level Chip Scale Package (WLCSP) has been widely used in MEMS and SiP packages; application of mobile and consuming products. It advantages in lightweight, reducing manufacturing cost, low I/O density and high performance because the bumps directly interconnect between die and motherboard. However, the lower Temperature Cycling on Board (TCoB) reliability performances because of CTE mismatches between die and test board was more and more serious for increasing WLCSP package size, especially the size is larger than 6mm × 6mm, the first failure temperature cycle count will below 600 cycles. In this study, both experimental method and Finite Element Method (FEM) simulation will be used to enhance large size WLCSP performance in TCoB reliability test. We will analyze WLCSP structure with Bump Support Film (BSF) to find out the optimum thickness in stress viewpoint by FEM simulation, the board level experiment result and failure phenomenon will be figured out as well.
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