Board Level Reliability assessment of Wafer Level Chip Scale Packages for SACQ, a lead-free solder with a novel life prediction model

Abstract

Smart devices nowadays require more functionality in the integrated circuits with smaller packages. Wafer Level Chip Scale Package (WLCSP) is one of a best choice in the industry due to their small size and functionalitz. However, the reliability of such WLCSPs is very critical as they are used in consumer products. With new solder alloy material, SACQ (Sn92.45% / Ag4% / Cu 0.5% / Ni 0.05% / Bi 3%), it is vital to have a reliable life prediction mode for the Wafer Level Chip Scale package family. At the current industry trend, there is no much reliability assessment of WLCSPs using this new solder alloy. Even, if some exists, the accuracy between the board level reliability qualification test and numerical simulation is still more than 10% tolerance. In this work, a fatigue model is developed for SACQ for wafer level package family with the help of board level reliability qualification test; statistical approach and numerical approach using Finite Element Method (FEM) leading to a close correlation between the measured characteristic life time from temperature cycling on board (TCoB) tests and predicted life from numerical method. In this paper, a fatigue life prediction model for SACQ is introduced after studying five different wafer-level chip scale packages (WLCSP) subjected to Board Level Reliability (BLR) Temperature Cycling Qualification Tests (TCT). Number of solder interconnects (IOs) or pincounts in the wafer level packages ranges from 182 IOs till 360IOs. Temperature cycling range between - 40°C till +85°C is applied to samples, until significant solder joint fatigue failures are observed. A Weibull lifetime model is used to describe the BLR qualification test data. In order to validate BLR-TCT qualification, several numerical simulations are carried out based on Finite Element Method (FEM). Anand viscoplasticity material constitutive law is used for SACQ. Increment of volume averaged inelastic strain energy density is used as damage parameter in order to determine the fatigue life prediction model. This new fatigue life prediction model developed demonstrates that the relative error of the predicted life time for the wafer level chip scale package (WLCSPs) with the new lead-free solder is within relative error of 10% with respect BLR-TCT tests. Such a close correlation between measurement and numerical simulation for SACQ solder is illustrated first time in industry for WLCSP package family. This research work can answer the reliability challenges faced in WLCSP packages with SACQ as solder material and the future work will be based on impact of underfills on WLCSP device reliability with SACQ as solder material.