A high-linearity 6-GHz phase interpolator in 28-nm CMOS technology

Abstract

This paper represents a wide-band low-power phase interpolator(PI) with high-linearity phase steps designed for Mobile industry Processor Interface(MIPI) standards like Multi-media Physical layer (MPHY) High speed Gear 2 that operates at 3GBps to HS-Gear 4 that operates at 6Gbps. The proposed PI consists of an input current-starved circuit for slew rate control, a core PI with cross coupled and diode connected loads, CML-to-CMOS output circuit, and a PI digital controller. The differential non-linearity(DNL) and integral non-linearity(INL) are within 0.15 LSB and 0.27 LSB respectively, The circuit is implemented in a 28-nm CMOS technology and operates from 1.5 to 6 GHz. The circuit consumes 2.2 mW from 0.9-V supply when operates at 6 GHz.