Abstract
A 14GHz CML-based phase interpolator (PI) is proposed for a 4-way time-interleaved 56Gbaud clock and data recovery (CDR). The phase interpolator has a resolution of 7 bits and is implemented in 28 nm CMOS technology with a 1.0V power supply. The proposed PI consists of a PI controller, a slew-rate-control buffer, and a phase mixer. The distribution of the tail current sources, short-channel effect, and the slew rate of the input signals are analyzed and several methods are proposed to optimize the interpolation linearity. The measured integral non-linearity (INL) and the calculated differential non-linearity (DNL) are less than 1.20 LSB and 0.27 LSB respectively at 14GHz. The total power consumption is 8.48mW.
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