A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

Daniel Junehee Lee

doi:10.32920/ryerson.14652180

Abstract

<p>The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.</p>

Highlights

ADCs play an important role in virtually every aspect of our daily life
This paper presents an area and power-efficient digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) along with comprehensive reviews of the state-of-the-art of DTCs and digital phase interpolator (PI) to be used for DTCs
The 8-bit DTC to be used for a time-mode successive-approximation register (SAR) ADC with a minimum power consumption and silicon area was presented

Summary

Introduction

ADCs play an important role in virtually every aspect of our daily life. Among various architectures of ADCs, a flash ADC, a delta-sigma ADC, and a SAR ADC are dominant. Flash ADCs offer the highest conversion rate and are widely used in applications such as high-speed data links over electrical and optical channels. The exponentially rising silicon area and power consumption with bit resolution and stiff challenges encountered in battling comparator mismatch limit the resolution of these ADCs. Delta-sigma ADCs offer the highest resolution by means of oversampling and noise-shaping. The emerging applications of SAR ADCs range from biomedical instruments where power consumption is of a great importance [4] to high-speed data links where conversion rate is pivotal [5, 6], largely accredited to the full compatibility of SAR ADCs with technology scaling [7]. TIME-MODE CIRCUITS the overall power consumption and silicon area, is sharply confronted with a rising noise floor and the deteriorating effect of clock feed-through and charge injection. Time-mode circuits possess a number of unique characteristics such as full compatibility with technology scaling, full programmability and portability, and a rapid design turn-around time which are not possessed by their analog counterparts [25]

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Results

Conclusion