A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

Abstract

This paper presents a high-density,129-channel, dual-‘hit’ FPGA-based time-to-digital converter (TDC) developed to implement the trigger-less data acquisition (DAQ) system for the Iron Calorimeter (ICAL) detector of the India-based Neutrino Observatory (INO) experiment. In this trigger-less DAQ scheme, the arrival time of signals from all the detector channels, about 3.6 million channels in the case of the INO-ICAL experiment, is required to be measured. This work, therefore, aimed at the development of a low-power, high-density TDC with uniform performance across the channels in the low-cost Spartan-6 FPGA. This TDC is based on tapped delay line (TDL) interpolation technique built using CARRY4 elements of the FPGA in the Spartan-6 FPGA-based DAQ system. In this TDC, a method for measuring the time-of-arrival of both the rising edge and subsequent falling edge (dual-hit) using a single channel is developed, thus allowing pulse width measurements. Here, a resource and power-aware design methodology is developed to arrive at the optimum values of the total number of delay elements in the TDL and clock frequency, facilitating the implementation of a large number of identical TDC channels. Further, in order to meet the area and timing constraints of the high-density TDC, semi-automatic placement scripts are developed with careful partitioning of the TDC channels. These aspects resulted in an implementation of the TDC with a least significant bit (LSB) resolution of 84.4 ps ± 2.5 ps, a dynamic range of 40 μs, time precisions (σ) across the channels in the range of 42 ps (0.49 LSB) to 58 ps (0.68 LSB), differential nonlinearity (DNL) of ±0.5 LSB and integral nonlinearity (INL) of [-0.49,0.84] LSB with a low power consumption of 7 mW per channel.