An FPGA based 33-channel, 72 ps LSB time-to-digital converter

Abstract

This paper describes a 33-channel time-to-digital converter (TDC) implemented in FPGA. This TDC is developed for the time-of-flight measurements using resistive plate chamber (RPC) detectors in India-based Neutrino Observatory (INO) experiment. The 33-channel TDC is implemented in Xilinx Spartan-6 FPGA using flash architecture by utilizing the carry-chains of the FPGA. The TDC features a novel bit latching scheme for fine interpolators to avoid overwriting of the delay line bits. The TDC also implements a low resource-consuming calibration method to achieve stable resolution under PVT variations in multi-channel TDC implementation. The TDC has the least significant bit (LSB) resolution of ∼72.4 ps across the channels with 20 μs dynamic range. The differential non linearity (DNL) and integral non linearity (INL) over 20 μs dynamic range are ±0.56 LSB and [−0.86, 0.76] LSB respectively. The TDC consumes a power of 12.12 mW per channel. All 33-channels are characterized; the channel-to-channel variation in precision is ∼3 ps. The precision of the pulse width measurements is ∼39 ps. This paper discusses various aspects of the TDC implementation.