Abstract
A high-speed CMOS phase/frequency detector (PFD) for faster frequency acquisition is presented. An improved CMOS D-type master-slave flip-flop is described and adopted. Higher speed is attributed to the reduced node capacitances. Charge-sharing phenomena are circumvented. An input delay scheme is employed to achieve faster acquisition. The optimal delay for PFD maximum operating frequency is analytically studied and a design guide is given.
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