Abstract
A CMOS phase/frequency detector (PFD) for faster frequency acquisition is presented. An improved CMOS D-type master-slave flip-flop is described and adopted in the PFD. Higher speed and lower power operation is attributed to the reduced node capacitance. Charge-sharing phenomena are circumvented in the proposed flip-flop and PFD. The proposed PFD shows improvements in both phase and frequency sensitivities at high operating frequency. HSPICE simulations of a phase-locked loop (PLL) employing the improved PFD demonstrate a faster frequency acquisition
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