Abstract
AbstractPerformance and comparison of several architecture topologies involve low phase noise and high-speed phase frequency detector. Phase frequency detector is essential in Phase-Locked Loop. Phase frequency detector has many advantages over Phase detector (PD) and Frequency detector (FD) by detecting frequency and phase simultaneously. Charge pump based phase frequency detector is an important block for signal generation in the PLL. At higher frequencies, the challenges like phase noise, jitter, power consumption, and area arise. This article discusses these design challenges of phase frequency detector at higher frequencies. Parameters of different design topologies have been compared. This comparative study will help the researchers to choose the best design out of the given topologies.KeywordsPhase frequency detectorCharge pumpPhase-locked loop
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