Abstract
The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient way of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan chain. In this paper, we propose a graph‐based approach to a stitching algorithm for automatic and optimal scan chain insertion at the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity information from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem to determine the best scan‐stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis and implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.
Highlights
The design flow of an integrated circuit (IC), meaning the software applications that allows the designer to move from its specification to its concrete realization, involves many stages of optimization problems, usually from system level to layout [1,2,3]
The main contributions of the paper are summarized below: (i) we analyze what is a suitable objective for measuring the quality of scan stitching orderings, (ii) we give a mathematical formulation of the problem of scan insertion at the register transfer level (RTL), (iii) we give two reduction procedures to solve the severalchains variants based on a routine solving the onechain case, (iv) we solve the one-chain case in a two-steps approach, (v) we evaluate our algorithm on both academic and industrial designs
Our algorithm provides a basis for considering the implementation of scan chains as soon as the Register Transfer Level (RTL) of a block is available; the authors think that the lack of optimization has been a big obstacle to its adoption in design flows
Summary
The design flow of an integrated circuit (IC), meaning the software applications that allows the designer to move from its specification to its concrete realization, involves many stages of optimization problems, usually from system level to layout [1,2,3]. The circuit must meet flawlessly customer expectations in terms of functionality, speed, quality, reliability, and cost. In such a challenging economic environment, and given the significant level of complexity which is reached by the IC, manufacturing testing is more than ever an important factor in the design problem
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