A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency

Abstract

A new Parallel Prefix Adder (PPA) based on the Ladner-Fischer is presented in this paper. The logic level of the proposed adder same as Ladner-Fischer is equal to "(logN)+1". The cell fanout in the critical delay path of Ladner-Fischer is reduced in the proposed design. Delay is improved in the proposed adder because of equal logic level in both of Ladner-Fischer with fewer cells fanout in the critical delay path of proposed structure and this delay improvement grows continuously by increasing the bit-width. Also, using full-swing Pass Transistor Logic (PTL) instead of CMOS cells for improving the performance of adders is presented in this paper. The outputs of PTL gates same as CMOS cells are always strong “0” and “1”, also the power and delay of CMOS cells are enhanced in full-swing PTL gates. The simulations are performed in 65nm/180nm standard CMOS technologies. According to the simulation results, the average improvement in Power-Delay-Product (PDP) of proposed adder than Ladner-Fischer with PTL cells (16, 32, 64, 128, and 256-bit) in 65nm(180nm) is 24.869%(24.586%).