A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

Abstract

This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout ( $\Delta $ -readout) scheme reads the signal difference between two pixels located next to each other ( $\Delta _{\mathrm {pixel}}$ ) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by the $\Delta $ -window checking, the proposed $\Delta $ -readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a $0.18~\mu \text {m}~1$ P4M CIS process with a $4.4~\mu \text {m}$ pixel pitch, where each single ADC occupies an area of $70\,\,\mu \text {m}\,\,\times \,\,500\,\,\mu \text {m}$ . The measurement results of the implemented prototype CIS showed a maximum power-saving of 26% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step.