11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors

Abstract

A first-step half-reference ramping (FHR) readout scheme is presented in this study for high frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the conversion speed of a single-slope (SS) analog-to-digital converter (ADC) by applying a binary-weighted searching algorithm at the first A/D conversion attempt. By effectively reducing the reference signal range, the proposed FHR readout scheme can reduce the number of A/D conversion steps in the SS ADC while maintaining the ADC performance. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed FHR scheme becomes more effective as the bit-depth of the ADC increases. A prototype CIS with a column-parallel 11-bit SS ADC was fabricated in a 0.11- $\mu \text{m}$ 1P4M CIS process with a 2.9- $\mu \text{m}$ pixel pitch. A maximum frame rate of 570 frames/s was achieved with a $1024\times240$ pixel resolution, corresponding to a 140.08 Mp/s pixel rate. Total power consumption was 57.2 mW under 2.8 V for pixel readout and 1.8 V for readout circuitry. When compared with the conventional 11-bit SS ADC, the proposed FHR scheme shortens the total A/D conversion time by 38.4%. The prototype CIS demonstrated the figure of merits (FoM) of 0.84 $\text{e}^{-}\cdot $ nJ and 0.41 $\text{e}^{-}\cdot $ nJ/step.