Abstract
While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.
Highlights
Recent advances in semiconductor manufacturing technologies have caused the development of improved designs that contain faster and more diverse functions
We propose a debug scheme that applies hierarchical compaction using multiple multiple-input signature registers (MISRs) and that improves the error identification capability in comparison with that used in the previous techniques
In the proposed debug scheme, the high-level MISR signatures are compared with the golden signatures in the trace buffer using an on-chip comparator to predecide the error-suspect debug intervals
Summary
Recent advances in semiconductor manufacturing technologies have caused the development of improved designs that contain faster and more diverse functions. In the proposed debug scheme, the high-level MISR signatures are compared with the golden signatures in the trace buffer using an on-chip comparator to predecide the error-suspect debug intervals.
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