Abstract
Post-silicon debug has become important with the increased complexity of circuit designs. However, the increase in debug resource costs owing to improved observability has posed a major challenge. To overcome this challenge, this study proposes on-chip error detection that reuses built-in self-repair (BISR). The proposed method utilizes the components of BISR as storages of golden signatures and comparators for error detection. Also, it detects error-suspect cycles more precisely by using parent and child multiple-input signature registers (MISRs). In addition, it provides selective capture and store methods that selectively capture error-suspect debug data in buffers and store them in the DRAM, respectively. The experimental results of various debug cases demonstrate that the proposed method significantly reduces the buffer size, DRAM usage, and debug time compared to previous methods.
Highlights
With the advance of very large scale integration technology, the density and capacity of integrated circuits has rapidly increased
EXPERIMENTAL RESULTS This section discusses the experimental results in terms of dynamic random-access memory (DRAM) usage, debug time, and hardware area overhead to describe the benefits of the proposed silicon debug method that reuses content addressable memories (CAMs) in built-in self-repair (BISR)
It is reasonable since three-dimensional integrated circuits (3D-ICs) have been introduced by integrating a system-on-chip (SoC) die and multiple dynamic random-access memory (DRAM) dice with short and dense through-silicon vias (TSVs)
Summary
With the advance of very large scale integration technology, the density and capacity of integrated circuits has rapidly increased. This study proposes on-chip error detection reusing BISR, which is utilized during memory test and repair in manufacturing, for a cycle-accurate deterministic debug environment for a 3D-IC. The main objective of the deterministic phase is to detect the root cause in terms of space (erroneous logic) and time (exact clock cycle when the debug occurs) information as rapidly as possible by using golden data calculated through simulations using the behavioral model of the circuit [15]–[18]. 3) The DfD operation by reusing BISR is introduced to perform DRAM-based on-chip error detection It overcomes the challenge of communication between the DfD and the DRAM, which is caused by using the components of BISR as buffers.
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