Massive signal tracing using on-chip DRAM for in-system silicon debug

Abstract

Silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. We propose a low-cost debug architecture for massive signal tracing in ICs that integrate fast DRAM, such as 2D-ICs with embedded DRAM or 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. During a debug session, the entire observation window is divided into intervals and a signature is calculated for each observed interval using a multiple-input signature register. At run time, intervals containing erroneous bits are identified by comparing their signature with pre-calculated “golden” signatures that are stored in the DRAM a priori. Only failing intervals including their time stamp are stored into DRAM, which allows for a more efficient use of the memory, resulting in a larger observation window. The proposed method does not require multiple iterations or intermediate processing steps, hence it can be used during functional testing with minimum time overhead associated with the upload of golden signatures and the download of stored debug data to external equipment. We have created a Verilog RTL model for the proposed architecture, synthesized it using a 45 nm CMOS library, and verified its functionality by simulation. The results show that the observation window can be increased by orders of magnitude compared to prior work at comparable hardware cost.