A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation

Abstract

Satisfiability(SAT)-based error diagnosis during presilicon verification has been quite successful. Recently, SAT-based debugging for error localization in the post-silicon environment has also been attempted. Analysis of silicon debug data is challenging because of the limited observability of the internal signals, which leads to elongating the error localization process. Therefore, the success of the debug process in the post-silicon scenario depends on effective on-chip tracing of internal signals of the design. This paper proposes a grouping based signal tracing methodology for collecting useful debug data from chip execution. The proposed methodology analyzes logical connectivity in the design netlist for deriving different signal groups from which a limited number of signals are traced. Effective post-silicon debug data is collected with the proposed signal selection scheme and an SAT-based debugging methodology is applied for analysis of these traces. Experiments on benchmark circuits show that the proposed internal signal grouping and the debug process is effective for localizing functional and electrical errors.