A cost-effective approach to implement a long instruction word microprrocessor

Abstract

This paper presents a cost-effective approach to implement a long instruction word microprocessor. The proposed approach achieves the goal of optimal performance/cost tradeoff by selectively, instead of unconditionally, duplicating the hardware resources in a uniprocessor. A hardware resource is duplicated only if the performance improvement gained by doing so can justify the cost incurred. In accordance with this guideline, a long instruction word microprocessor architecture called the MPA architecture is proposed. The MPA architecture has two parallel execution units and, with a minimal increase of hardware cost, delivers a performance significantly higher than that of a RISC (Reduced Instruction Set Computer) uniprocessor, more than 50% higher in average for the five benchmark programs used in this sutdy. On the other hand, a long instruction word microprocessor with everything duplicated delivers a performance just slightly higher than that of the MPA architecture, less than 1% higher in average for the same five benchmark programs, but the cost incurred is a lot higher.