Abstract
In October of 1991, IBM, Apple, and Motorola formed an alliance to produce a new microprocessor family named the PowerPC. Less than two years later, the alliance has produced the first chip of the PowerPC family, the MPC601. The paper analyzes the PowerPC 6xx family, with an emphasis on the architecture of the MPC6O1 chip. The 601's Reduced Instruction Set Computer (RISC) architecture is examined, including the three parallel execution units (integer unit, branch unit, and floating point unit), the instruction unit, the memory management unit, and the system interface. In addition, the software environments for the PowerPC are discussed. Finally, conclusions about the chip are drawn and an outlook on the future of the PowerPC family is made. >
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
