Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors

Abstract

The design of an instruction set architecture (ISA) plays an important role in exploiting processor resources and providing a common software interface. Three main classes of ISAs can be distinguished: complex instruction set computer (CISC), reduced instruction set computer (RISC), and very long instruction word (VLIW). They differ mainly in assembler and compiler support, pipeline control, hardware requirements, and code density. The main disadvantage in many applications is code size explosion. To reduce code size, a method called tagged VLIW (TVLIW) is presented in this chapter. Dividing the instruction set into control/move and arithmetic instructions, a different usage of functional units can be examined. The first set only requires the parallel execution of a limited number of functional units. The second set, though requiring several functional units in parallel, is often used inside loops. Within the method proposed by the chapter, the instruction word is dynamically assembled using a low complex highly regular decoding hardware. Inside loops, the full VLIW functionality is supported by cache methods.