A Compact Half Select Disturb Free Static Random Access Memory Cell with Stacked Vertical Metal–Oxide–Semiconductor Field-Effect Transistor

Abstract

In this paper, a half select disturb free compact static random access memory (SRAM) cell with the stacked vertical metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed, and the impacts on its cell size, stability and speed performance are evaluated. The proposed SRAM cell has a small cell size, which is 67% of the conventional eight-transistor (8T) SRAM cell, because of its stacked vertical MOSFET structure. It realizes a half select disturb free SRAM operation; therefore, a larger static noise margin of 5.9 times is achieved in comparison with the conventional 8T SRAM cell. It suppresses the degradation of the write margin, thus its write margin is 84.2% of the conventional 8T SRAM cell. Furthermore, it suppresses the degradation of the write time by 39% (0.249 ns). The proposed compact SRAM cell with the stacked vertical MOSFET is a suitable SRAM cell with a small cell size, immunity to the half select disturb, wide write margin and fast write time.