A CMOS latch circuit for multiple-valued bi-directional current signals

Abstract

Abstract A new latch circuit for bi-directional multiple-valued logic (MVL) current signals has been realized in a standard 2-microri poly-silicon gate CMOS process. The circuit accepts and quantizes a bi-directional input current during the SETUP clock phase and latches the quantized input during the HOLD clock phase. Using logical current increments of only l0μA, the bi-directional current-mode MVL latch set-up and hold time has been determined to total approximately 45 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 45 ns at these low current levels.