Abstract
A proposed phase-interpolator (PI) based hybrid digital pulse width modulator (DPWM) effectively resolves the trade-off between resolution and power consumption. Conventional DPWM delay-line-based architectures suffer from high power consumption limited delay time per delay-tap due to process technology, while the proposed solution replaces the delay line with a PI featuring sub-gate-delay resolution. To address the issue of the increase of area when using a conventional PI, a zooming scheme is proposed. Since the proposed architecture consists only of static circuitry, zero-quiescent power, wide operating voltage range, and instantaneous start-up are provided. A prototype chip manufactured with 0.13-pm BCD technology achieves 762-pW power consumption at 16.3-ps resolution and 10-MHz switching frequency, with 1.2-V supply voltage. With 0.75-V supply voltage, 163-ps resolution and 1-MHz switching frequency is achieved with 36-pW power dissipation.
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