Abstract

This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines' process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.

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